Intel Nehalem Microarchitecture

NEHALEM Features:
 Intel Quick path Architecture
 High-k process technology
 45nm presently and 32nm in future
 Inclusive last level cache
 SSE4.2
 Loop stream detector
 Simultaneous multi threading

These features are explained below…

One of the key features that NEHALEM has is the Quick path architecture. The two components are quick path memory controller and quick path interconnect. As memory controllers are integrated along with the processors the Bandwidth is increased rapidly boosting speeds of data input for the CPU’s. This also helps in integrating multi processor.

Intel Nehalem is built with Industry’s first, High Density transistor with High-k process technology coming in 45nm. The traditional Silicon Gate and Silicon Dioxide insulator is removed in transistors because for the electron leakage problem and comes equipped with Metal gate and Hafnium insulator. This Technology can power Notebooks, Desktop to High end Servers with energy efficiency.

Inclusive last level cache is introduced in Nehalem. This improvement eliminates unnecessary core snoops to reduce latency and improves cache performance. The older method is slower called Exclusive level cache.

Nehalem has 7 instructions set including 4 of SSE4.2. This helps better text and string processing boosting performance for XML parsing (communication protocol). Compared to older CPU’s, which reads text, bit by bit. The new feature lets us compare text in length of 16 bytes. This ultimately reduces the state transitions requirement.

The Loop stream detector identifies repetitive instruction sequences and queues the loop without getting it again from the source. This reduces power as it gives rest for other branch prediction, fetch and decode units.

Advanced features of Nehalem micro architecture are increased parallelism, more efficient algorithm and improved branch prediction.

Nehalem has a great feature called Simultaneous multithreading (SMT). It helps to run 2 threads per core. In Normal QUAD core processor, it sends data to cores which will process one thread per core. But with SMT present day multicore processors handle 8 threads (2 per core). future plan is to increase up to 16 threads. Just adding more and more Cores is not energy efficient way, with SMT we can increase the threading. This gives higher and higher performance for the growing needs of application. Ultimately reduces power consumption.

The full featured Nehalem is expected to be launched in November or December 2008. The Next generation 32nm processors will come later.